Portapack-Carnage

◆ RCC_CFGR_PLLXTPRE_HSE_Div2

#define RCC_CFGR_PLLXTPRE_HSE_Div2   ((uint32_t)0x00020000)

#include <firmware/chibios/os/hal/platforms/STM32F1xx/stm32f10x.h>

HSE clock divided by 2 for PLL entry